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FPGA Design Verficiation Engineer

Trinamics Beheer B.V. - Eindhoven
Functieomschrijving Developing and managing UVM test benches for FPGA-based hardware designs. Creating and executing detailed test plans to validate the functionality of FPGA devices. Continuously improving verification
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Lead MTS Logic Design

Rambus - Vught
innovative ideas/patents for current and future productsImplementation: RTL design, lint, clock domain crossing (CDC) analysis, synthesis, IP releaseVerification: work with verification team on planning and execution, simulation
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Digital ASIC Design Engineer

Trinamics Beheer B.V. - Eindhoven
Develop and maintain test scripts to automate the verification process. Perform verification across process corners and with post-layout designs. Collaborate with mixed-signal verification engineers. Functie-eisen 5+ years of
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