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Vacatures 721 tot 730 van 827 (ontdubbeld 825)
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Senior Backend Developer

Lely - Maassluis
Vacatureomschrijving We zijn op zoek naar een getalenteerde en ervaren Senior Back- End Developer om ons team te versterken en een sleutelrol te spelen in het ontwerp, de ontwikkeling en het onderhoud van onze Portal en
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Werkvoorbereider medior Installatietechniek

Building Heroes - Rotterdam
Be a hero Als medior werkvoorbereider bij onze relatie ben jij de spil in het voorbereiden en coördineren van onze high- end projecten. Je werkt nauw samen met projectleiders, uitvoerders en andere belanghebbenden om ervoor
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Werkvoorbereider Senior Installatietechniek

Building Heroes - Rotterdam
Be a hero Als Senior werkvoorbereider bij onze relatie ben jij de spil in het voorbereiden en coördineren van onze high- end projecten. Je werkt nauw samen met medior/junior projectleiders, uitvoerders en andere
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IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview

IP Security & Digital Design Expert (ASIC)

Jobs in Security - Rotterdam
cryptographic co-processors, secure memories, secure elements, smart cards) Familiarity with front - end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence
FULL_TIME - Preview