Vacatures 1 tot 10 van 132
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Yacht - Veldhoven
represents nearly 30% of ASML’s procurement costs. The two maintain a strategic alliance requiring a three-year notice for termination. ASML heavily invests in R&D. Functieomschrijving FPGA Firmware designer responsibilities:- The- Volledige vacature bekijken
Brunel - Eindhoven
IntroductieOur client is responsible for designing and producing high-tech machines and machine modules. They are expanding their business, therefore we are looking for a FPGA / VHDL Firmware Designer who will empower the- Volledige vacature bekijken
Brunel Nederland B.V. - Eindhoven
documenting requirements, implementing and simulating VHDL code as well as testing the firmware in test setups and in the machine module. As a FPGA Designer you are the first point of contact for questions related to this topic. In the- Volledige vacature bekijken
Randstad - Veldhoven
MBO,HBO ASML Netherlands B.V. solliciteer via YACHT functieomschrijving 07 februari 2025 vacaturenummer: 9175969 07 februari 2025 vacaturenummer: 9175969 FPGA Firmware designer - Preview - Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan
Tmc via Talent - Eindhoven
optimisation, VHDL/Verilog/SystemVerilog/UVM, DFT, digital modelling ofanalogue IPs, FPGA prototypingCadence design tools knowledge is a preferenceExcellent understanding of verification challenges and the ability to support- Opslaan
Tmc via Talent - Eindhoven
front-end chip and currently an FPGA . We are looking for support to design the FPGA sub-system. Though the RTL is currently used only in FPGA , it should be suitable for ASIC too. So, the use of FPGA -specific IPs is NOT- Opslaan