Vacatures 1 tot 10 van 24
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Brunel Nederland via Brunel - Eindhoven
Our client is responsible for designing and producing high-tech machines and machine modules. They are expanding their business, therefore we are looking for a FPGA / VHDL Firmware Designer who will empower the electronics- Volledige vacature bekijken
Yacht - Veldhoven
Firmware designer responsibilities:- The FPGA Designer reports to the Group Manager Electronics EUV or delegated Team Leader. Participate as an FPGA Firmware designer in a multidisciplinary design team. Define and document- Volledige vacature bekijken
Witteveen+Bos - Breda
geïntegreerd en slim ontwerp te komen waarin tegemoet gekomen wordt aan de wensen en de eisen van onze opdrachtgevers. Jouw rol als virtual structural designer is om samen in een team met constructeurs, geotechnici en de ontwerpleider- Volledige vacature bekijken
Yacht - Veldhoven
FPGA Firmware designer responsibilities:- The FPGA Designer reports to the Group Manager Electronics EUV or delegated Team Leader. Participate as an FPGA Firmware designer in a multidisciplinary design team- Preview - Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan
Randstad - Veldhoven
MBO,HBO ASML Netherlands B.V. solliciteer via YACHT functieomschrijving 07 februari 2025 vacaturenummer: 9175969 07 februari 2025 vacaturenummer: 9175969 FPGA Firmware designer - Preview - Opslaan
European Tech Recruit via Talent - Vught
data transfer, pushing the boundaries of what’s possible with both chip and IP technology. As a Senior Logic IP Designer , you will lead the design of secure silicon IP, including RTL design, clock domain crossing (CDC) analysis- Opslaan